1. Field of the Invention
Briefly described, this invention relates to an improved method for fabricating a p-i-n semiconductor photodiode that results in improved uniformity and device scalability over large substrate sizes.
2. Description of Related Art
Linear and 2-D arrays of InGaAs p-i-n photodiodes are commercially important for a wide range of applications. Linear arrays are used as wavelength monitors for wavelength division multiplexing (WDM) communication systems (C. Koeppen, J. L. Wagener, T. A. Strasser, and J. DeMarco, xe2x80x9cHigh resolution fiber grating optical network monitor,xe2x80x9d Proc. National Fiber Optic Engineers Conference, 1998.), spectroscopy (G. H. Olsen, xe2x80x9cInGaAs Fills the Near-IR Array Vacuum,xe2x80x9d Laser Focus World 27, p. 48 (1991)), and machine vision applications. Two-dimensional arrays are used in many applications ranging from surveillance to industrial process control. Linear photodiode arrays are available with up to 512 elements, while 2-D arrays are available with up to 320xc3x97240 elements. These devices are large in comparison to most semiconductor devices. A 512 linear array is 2 cm in length and a 2-D array is also large, with a 320xc3x97240 array being 1.3 cmxc3x971 cm. This large device size drives the need for a device structure and process which is uniform and scalable with substrate size. Conventional methods of device fabrication used a vapor-phase Zn diffusion to define the device active region.
Increasing substrate sizes characterizes the history of semiconductor fabrication. This increase in size is driven by the cost effectiveness of scaling the process to larger and larger wafer sizes. The trend is particularly true of more complex devices containing large numbers of devices, such as transistors. The compound semiconductor industry is driven by a similar trend as the devices fabricated from these materials contain a larger number and size of elements such as transistors and diodes. The GaAs industry has scaled wafer sizes from 2 inch diameters (50 mm) up to 6 inches (150 mm) in recent years as the chips fabricated from this material have achieved increasing levels of device integration. The InP-based materials systems are experiencing a similar pressure to increase the substrate size to take advantage of the cost advantages of larger wafer sizes.
As the wafer size is increased, the processing of the devices becomes more challenging. To take advantage of the larger wafer size, the process must scale with the area of the wafer. The invention discussed herein addresses the problem of scaling the diffusion of impurities to large wafer sizes.
The following patents may be generally relevant to the state of the art and the present invention.
U.S. Patent entitled xe2x80x9cPhotodetectorxe2x80x9d (U.S. Pat. No. 4,597,004) describes a photodetector in which the preferred embodiment is structured with a non-patterned p-contact layer, and in which a buffer layer is added to prevent excess diffusion from the p-doped layer.
U.S. Patent entitled xe2x80x9cPhotovoltaic Diode with First Impurity of Cu and Second of Cd, Zn, or Hgxe2x80x9d (U.S Pat. No. 3,836,399) describes a device in which the diffusion is over a broad area and for which no specific method or patterned structure is indicated.
U.S. Patent entitled xe2x80x9cEnhancement of Photoconductivity in Pyrolytically Prepared Semiconductorsxe2x80x9d (U.S. Pat. No. 4,616,246) describes a device prepared using n-type layers grown, but not subsequently patterned or diffused, to fabricate the device.
U.S. Patent entitled xe2x80x9cBuried Heterostructure Devices with Unique Contact-Facilitating Layersxe2x80x9d (U.S. Pat. No. 4,661,961) describes a fabricated device in which the contact layers are patterned by growth of additional material to define the device active region.
U.S. Patent entitled xe2x80x9cPassivation of InP by Plasma-Deposited Phosphorusxe2x80x9d (U.S. Pat. No. 4,696,828) shows a method for passivating surface states using a phosphorus layer.
U.S. Patent entitled xe2x80x9cLateral P-I-N Photodetectorxe2x80x9d (U.S. Pat. No. 4,746,620) describes a device in which the p-type and n-type regions of the photodiode are defined by alloying doped metallic contacts onto the semiconductor substrate.
Finally, U.S. Patent entitled xe2x80x9cPIN Junction Photovoltaic Element with p or n-type Semiconductor Layer Comprising Non-Single crystal Material Containing Zn, Se, H in an Amount of 1 to 4 Atomic % and Dopant and I-Type Semiconductor Layer Comprising On-Single Crystal Si(H,F) Materialxe2x80x9d (U.S. Pat. No. 4,926,229) describes a device fabrication process which uses non-single crystal and in which H is incorporated into the material.
The existing methods of scaling the diffusion of impurities into the semiconductor in order to define the device include sealed ampoule diffusion, open tube diffusion using a gaseous diffusion source, and the use of surface-deposited films of source dopant.
Sealed ampoule diffusion (Y. Yamamato, H. Kanabe, xe2x80x9cZn Diffusion in InxGa1xe2x88x92xAs with ZnAs2 Source,xe2x80x9d Japn. J. of Appl. Phys., vol. 19, No. 1, Jan 1980, pp. 121-128.) is characterized by the difficulty of handling large diameter quartz ampoules. In this method, the semiconductor wafer is sealed in a quartz ampoule containing a solid source of diffusion such as ZnAs2. The ampoule is placed on a high vacuum pumping system and evacuated to 10xe2x88x926 torr. The quartz ampoule is then sealed manually using an oxygen/hydrogen torch. The sealed ampoule is then placed in a furnace at the appropriate diffusion temperature. The deficiencies of this method include the manual handling problems involved with large diameter quartz, the large thermal mass requiring longer diffusion times, and the time consuming vacuum processing and sample preparation.
Open tube diffusion may be implemented in a number of different embodiments. Common to all of these embodiments (M. Wada, M. Seko, K. Sakakibara, and Y. Sekiguchi, xe2x80x9cZn diffusion into InP using dimethylzinc as a Zn source,xe2x80x9d Japn. J. of Appl. Phys., vol. 28, no. 10, October 1989, pp. L1700-L 1703; C. Blaauw, et al, xe2x80x9cSecondary ion mass spectrometry and electrical characterization of Zn diffusion in n-type-InP,xe2x80x9d J. Appl. Phys. 66 (2), 1989, pp 605-610; N. Arnold, et al, xe2x80x9cDiffusion in III-V semiconductors from spin-on film sources,xe2x80x9d J. Phys. D: Appl. Phys., 17, 1984, pp. 443-474.) is the requirement to maintain a sufficient overpressure of column V elements to prevent the compound semiconductor from decomposing at the temperatures required for impurity diffusion. This overpressure is usually achieved with the use of a gaseous source of phosphine (PH3) or arsine (AsH3). Both of these gases are extremely hazardous and require special handling, effluent control, licensing, and safety precautions. The cost of such gas handling is usually prohibitive and becomes more complex for larger and larger wafer sizes.
Spin-on diffusion sources are becoming more widely used (N. Arnold, R. Schmitt, K. Heime, xe2x80x9cDiffusion in III-V semiconductors from spin-on film sources,xe2x80x9d J. Phys. D: Appl. Phys., vol. 17, 1984, pp. 443-474.). They are scalable with device size and do not suffer the same requirements for column V overpressure as open tube or sealed-ampoule diffusion. This process does, however, suffer from the standard process variability common to all thin film deposition techniques. The source quality (freshness) and application to the substrate require precise control.
Diffuision is the preferred method of introducing impurities for p-i-n photodiode fabrication. The principal reason is that the material damage introduced by the ion implantation process causes defects that increase the dark current of the device (I. M. Tiginyanu, I. V. Kravetsky, V. V. Ursaki, G. Marowsky, H. L. Hartnagel, xe2x80x9cCrystal order restoration and Zn-impurity activation in InP by As++ plusxe2x80x94coimplantation and annealing,xe2x80x9d Physica Status Solidi (A) Applied Research v 162 n 2 August 1997. p R9-R10). Large dark currents are detrimental to photodiode performance for most applications.
In general, the prior art for diffusion of impurities are limited in process control and scalability. This invention addresses these problems in a completely scalable and controllable method.
The invention relates to photodetectors, principally p-n junction photodiodes, that are defined by the use of an epitaxially grown layer of semiconductor which is doped with the p-type impurity used to define the p-contact of the p-n junction.
Photodiodes, particularly in the array format, are required to be of uniform construction over large areas. The largest substrate diameter commonly available for manufacturing p-i-n photodiodes is 50 mm. One of the limiting steps of device definition is the diffusion of p-type impurity species that define the p-contact of the device. This disclosure proposes a method and the resulting device structure for photodiodes that uses a p-contact definition process and structure that is scalable to larger substrate sizes.
The solution consists of modifying the epitaxial growth to include a cap layer doped heavily with a p-type impurity, nominally Zn (the Zn source layer). This cap layer may consist of 1) InP, or 2) InGaAs lattice-matched to InP, or 3) of any one of a variety of ternary or quaternary III-V semiconductor alloys. This source layer is deposited epitaxially during the initial construction of the device. The Zn source layer is selectively removed by standard photolithography and etching in areas where no Zn diffusion is desired. The active device area where the Zn source layer remains will receive Zn diffusions upon annealing under the appropriate conditions, with appropriate encapsulants, typically SiNx. These conditions may include sealed ampoule diffusion, open-tube diffusion (with proper encapsulation), or rapid thermal annealing (RTA).
An InP source layer may be doped up to a level of approximately 1-3xc3x971018/cm3 without significant out-diffusion of during the epitaxial growth. Calculated diffusion into the underlying InP is less than 500 xc3x85. The InGaAs layer may be Zn-doped up to a level of approximately 1-3xc3x971019/cm3 without significant out-diffusion into the underlying layers during the epitaxial growth.
The process is planar, because the extent of the etch used to define the device will be only slightly larger than the extent of the Zn-source layer.
The invention may be more fully understood by reference to the following drawings.